FIG. 1 (Prior Art) is a simplified top-down diagram illustrative of a field programmable gate array (FPGA) integrated circuit 1. Integrated circuit 1 includes a ring of bond pads 2, an inner core of configurable logic blocks 3, and a fork-shaped clock distribution network 4. A clock signal present on a clock input pad 5 passes through a clock buffer 6, is distributed vertically through a vertical clock bus 7, passes through clock buffers 8-12, and then propagates horizontally from left to right through corresponding horizontally extending clock buses 13-17. In the bottom most clock bus 17, the clock signal propagates left to right from clock buffer 12, past point 18, and down the clock bus to point 19.
FIG. 2 (Prior Art) is a simplified cross-sectional diagram of a portion of integrated circuit 1 showing a section of clock bus 17. Numerous layers of Metallization 20 and dielectric material 21 are disposed over the substrate 22 of the integrated circuit 1. In the illustrated example, the metal of the clock bus 17 is insulated from other layers of metal above it and below it by dielectric material 21.
FIG. 3 (Prior Art) illustrates a series of RC trees 23 that is often used to model the propagation of a clock signal down such a clock bus. Points 18 and 19 in FIG. 3 correspond to points 18 and 19 in FIG. 1, respectively. The larger the resistance R, the longer it will take for the clock signal to propagate from point 18 to point 19. Similarly, the larger the capacitance C, the longer it will take for the clock signal to propagate from point 18 to point 19. Resistance R represents the distributed resistance of the clock bus being modeled. The capacitance C represents the distributed capacitance of the clock bus. The larger the dielectric constant K of the dielectric material separating the clock bus 17 from the other conductors of FIG. 2, the larger the distributed capacitance C.
In the example of FIG. 1, the propagation delay of the clock signal across the integrated circuit chip means that an edge of the clock signal will arrive at point 19 after it has arrived at point 18. This difference in time when the clock edge arrives is called "clock skew". In a digital integrated circuit, it is often desired to keep the magnitude of the clock skew within a certain percentage of the period of the clock signal. For example, it may be desired to keep the clock skew within ten percent of the clock period. A given clock edge is to arrive at all logic blocks within the same time period (ten percent of the clock period). A clock signal having a frequency of 500 megahertz has a period of two nanoseconds. Accordingly, in this example, if the clock signal is to arrive at all logic blocks within ten percent of the clock period, then the clock signal must be able to propagate across the integrated circuit in about two tenths of a nanosecond. Integrated circuits today can be 2.5 centimeters on a side and the locations where clock signals are required can easily be two centimeters apart. For the clock signal to travel two centimeters in two tenths of a nanosecond requires a propagation speed of about 10.sup.8 meters per second. Achieving such a high propagation speed across an integrated circuit is difficult.
Moreover, future advances in semiconductor processing technology are likely to lead to a desire to increase clock speeds into the gigahertz range. Such an increase in clock speed would further reduce the amount of time available for a clock signal to travel across an integrated circuit. Moreover, future integrated circuits may be even larger than integrated circuits of today. Such increases in size will likely result in the clock signal having to travel even greater distances. It is therefore foreseen that clock speeds of future integrated circuits may be limited by the propagation speed of clock signals on the integrated circuits.